esd5302f wi ll semiconductor ltd. 1 revision 1.2, 2014/09/03 esd5302f 2 - line s , un i - d irectional, ultra - low capacitance trans ient voltage suppressors descriptions the esd5302f is a n ultra - low capacitance tvs (tran sient voltage suppressor) array designed to protect high speed data interfaces. it has been specificall y designed to protect sensitive electronic components which are connected to data and transmission lines from over - stress caused by esd (e lectro s tatic d ischarge ) . the esd5302f incorporates two pair s of ultra - low capacitance steering diodes plus a tvs dio de. the esd5302f may be used to provide esd protection up to 2 0 k v (contact and air discharge ) according to iec61000 - 4 - 2 , and withstand peak pulse current up to 4 a ( 8/20 s ) according to iec61000 - 4 - 5. the esd5302f is available in sot - 23 package. standard pr oducts are pb - free and halogen - free. features ? stand - off voltage: 5 v max ? transient protection for each line according to iec61000 - 4 - 2 (esd) : 20 k v ( contact and air discharge ) iec61000 - 4 - 4 (eft): 40a (5/50ns ) iec61000 - 4 - 5 (surge): 4 a (8/20 s) ? ultra - low cap acitance: c j = 0.4 pf typ. ? ultra - low leakage current: i r <1na typ . ? l ow clamping voltage : v cl = 20 v @ i pp = 16a (tlp) ? solid - state silico n technology applications ? usb 2.0 and usb 3.0 ? hdmi 1.3 and hdmi 1.4 ? sata and esata ? dvi ? ieee 1394 ? pci express ? portable ele ctronics ? notebooks h ttp //: www. sh - willsemi.com sot - 23 ( top v iew) circuit d iagram w = will 02 = device code * = month code ( a~z) marking (top view) order i nformation device package shipping esd5302f - 3 /tr sot - 23 3 000/tape&reel 2 1 3 gnd 1 2 3 i / o 1 i / o 2 w 02 *
esd5302f wi ll semiconductor ltd. 2 revision 1.2, 2014/09/03 absolute m aximum r ating s electrical characteristics (t a =25 o c, unless otherwise noted) notes: 1) tlp parameter: z 0 = 50 , t p = 100ns, t r = 2n s, averaging window from 60ns to 80ns. r dyn is calculated from 4a to 16a. 2) according to iec61000 -4 -5. parameter symbol rating unit peak pulse power ( t p = 8/20 s) p pk 60 w peak pulse current (t p = 8/20 s) i pp 4 a esd according to iec61000 - 4 - 2 air discharge v esd 2 0 k v esd according to iec61000 - 4 - 2 contact d ischarge 2 0 j unction t emperature t j 1 25 o c operating temperature t op - 40~ 85 o c lead temperature t l 260 o c storage temperature t stg - 55~150 o c parameter symbol condition min. typ. max. unit rever se maximum working voltage v rwm 5.0 v reverse leakage current i r v rwm = 5v <1 100 n a reverse breakdown voltage v br i t = 1ma 7.0 8.0 9.0 v forward voltage v f i t = 1 0ma 0.6 0.9 1.2 v clamping voltage 1) v cl i pp = 16a, t p = 100ns 20 v dynamic resistance 1) r dyn 0. 65 clamping voltage 2 ) v cl i pp = 1a, t p = 8/20s 1 1 v i pp = 4 a , t p = 8/20s 1 5 v junction capacitance c j v r = 0 v, f = 1mhz any i/o pin to gnd 0.40 0. 6 5 pf v r = 0 v, f = 1mhz between any i/o pin 0. 25 0. 40 pf
esd5302f wi ll semiconductor ltd. 3 revision 1.2, 2014/09/03 typical characteristics (t a =25 o c, unless otherwise noted ) 8/20 s w a veform per iec61000 - 4 - 5 clamping voltage vs. peak pulse current non - repetitive peak pulse p ower vs. pulse time contact discharge current waveform per iec61000 - 4 - 2 capacitance vs. rever se voltage power derating vs. ambient t emperature 1 10 100 1000 1 10 100 1000 peak pulse power (w) pulse time ( s) 0 25 50 75 100 125 150 0 20 40 60 80 100 % of rated power t a - ambient temperature ( o c) 0 1 2 3 4 5 8 10 12 14 pulse waveform: t p = 8/20 s v c - clamping voltage (v) i pp - peak pulse current (a) t 60ns 30ns t r = 0.7~1ns 10 90 100 current (%) time (ns) 0 1 2 3 4 5 0.20 0.25 0.30 0.35 0.40 0.45 0.50 between pin1 and pin2 pin1 or 2 to pin3 f = 1mhz c j - junction capacitance (pf) v r - reverse voltage (v) 0 0 100 20 90 50 10 t 2 t 1 front time: t 1 = 1.25 t = 8 s time to half-value: t 2 = 20 s peak pulse current (%) time ( s) t
esd5302f wi ll semiconductor ltd. 4 revision 1.2, 2014/09/03 typical characteristics (t a =25 o c, unless otherwise noted ) esd clamping (+8kv contact discharge per iec61000 - 4 - 2) tlp measurement esd clamping ( - 8kv contact discharge per iec61000 - 4 - 2 ) 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 z 0 = 50 ? t r = 2ns t p = 100ns tlp current (a) tlp voltage (v)
esd5302f wi ll semiconductor ltd. 5 revision 1.2, 2014/09/03 application information the esd5302 f is designed to protect two high speed line against esd. fig1 is shown the connection and fig2 is shown pcb layout guide for usb interface esd protection fig1 fig2 vbus dm dp id gnd vbus dm dp id gnd
esd5302f wi ll semiconductor ltd. 6 revision 1.2, 2014/09/03 package outline dimensions sot - 23 symbol dimensions in millimeter dimensions in inches min. max. min. max. a 0.900 1.150 0.035 0.045 a1 0.000 0.100 0.000 0.004 a2 0.900 1.050 0.035 0.041 b 0.300 0.500 0.012 0.020 c 0.080 0.150 0.003 0.006 d 2.800 3.000 0.110 0.118 e 1.200 1.400 0.047 0.055 e1 2.250 2.550 0.089 0.100 e 0.950typ 0. 037 typ e1 1.800 2.000 0.071 0.079 l 0.5 5 0ref 0. 022 ref l1 0.300 0.500 0. 012 0. 020 0 8 0 8
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